// +FHDR----------------------------------------------------------
// Copyright (c) 2023, RJMicro Technology Co.,Ltd.
// RJMicro Confidential Proprietary
// ---------------------------------------------------------------
// FILE NAME       : .v
// DEPARTMENT      : IC Dept
// AUTHOR          :
// AUTHOR'S EMAIL  :
// ---------------------------------------------------------------
//
// Description     :
// 12'h000  STS
// 12'h004  CR
// 12'h008  CR1
// 12'h00C  MUX
// 12'h010  IER
// 12'h014  SR
// 12'h018  CLR
// 12'h01C  FILT
// 12'h020  FILT_DIA
// -FHDR
// ---------------------------------------------------------------

module ediag_regfile (
    input                  sts_out_sync        ,
    input                  sts_out_valid       ,
    input                  sts_w_out           ,
    input                  sts_v_out           ,
    input                  sts_u_out           ,
    input                  sts_ocd0_neg_filed  ,
    input                  sts_ocd0_pos_filed  ,
    input                  sts_ocd1_neg_filed  ,
    input                  sts_ocd1_pos_filed  ,
    input                  sts_level0_filed    ,
    input                  sts_level1_filed    ,
    input                  sts_uv15_filed      ,
    input                  sts_ov15_filed      ,
    input                  sts_uv50_filed      ,
    input                  sts_ov50_filed      ,
    input                  sts_otp_filed       ,
    input                  sts_brk_filed       ,
    output                 cr_en               ,
    output                 cr_mode             ,
    output                 cr_outsel           ,
    output [01:0]          cr_edgesel          ,
    output                 cr_oten             ,
    output [01:0]          cr_otsel            ,
    output                 cr_pga0_ocd_en      ,
    output                 cr_pga1_ocd_en      ,
    output [01:0]          cr_pga0_ocd_th      ,
    output [01:0]          cr_pga1_ocd_th      ,
    output [02:0]          cr_lpf              ,
    output [01:0]          cr_hys              ,
    output                 cr_offset           ,
    output                 cr_speed            ,
    output                 cr1_ocd0_neg_en     ,
    output                 cr1_ocd0_pos_en     ,
    output                 cr1_ocd1_neg_en     ,
    output                 cr1_ocd1_pos_en     ,
    output                 cr1_level0_en       ,
    output                 cr1_level1_en       ,
    output                 cr1_uv15_en         ,
    output                 cr1_ov15_en         ,
    output                 cr1_uv50_en         ,
    output                 cr1_ov50_en         ,
    output                 cr1_otp_en          ,
    output                 cr1_adc_otp_en      ,
    output                 cr1_brk_io_en       ,
    output                 cr1_level0_pol      ,
    output                 cr1_level1_pol      ,
    output                 cr1_brkio_pol       ,
    output [01:0]          mux_phsel           ,
    output                 ier_ie              ,
    output                 ier_leve0e          ,
    output                 ier_leve1e          ,
    output                 ier_ocd0_nege       ,
    output                 ier_ocd0_pose       ,
    output                 ier_ocd1_nege       ,
    output                 ier_ocd1_pose       ,
    input                  sr_pf               ,
    input                  sr_nf               ,
    input                  sr_levf0f           ,
    input                  sr_levf1f           ,
    input                  sr_ocd0_negf        ,
    input                  sr_ocd0_posf        ,
    input                  sr_ocd1_negf        ,
    input                  sr_ocd1_posf        ,
    output           clr_pfclr           ,
    output           clr_nfclr           ,
    output           clr_levf0clr        ,
    output           clr_levf1clr        ,
    output           clr_ocd0_negclr     ,
    output           clr_ocd0_posclr     ,
    output           clr_ocd1_negclr     ,
    output           clr_ocd1_posclr     ,
    output [09:0]          filt_fltdiv         ,
    output [04:0]          filt_fltwin         ,
    output [04:0]          filt_fltth          ,
    output [02:0]          filt_dia_ocd_neg_filt_sel,
    output [02:0]          filt_dia_ocd_pos_filt_sel,
    output [02:0]          filt_dia_level0_filt_sel,
    output [02:0]          filt_dia_level1_filt_sel,
    output [02:0]          filt_dia_uv15_filt_sel,
    output [02:0]          filt_dia_ov15_filt_sel,
    output [02:0]          filt_dia_uv50_filt_sel,
    output [02:0]          filt_dia_ov50_filt_sel,
    output [02:0]          filt_dia_otp_filt_sel,
    output [02:0]          filt_dia_brk_filt_sel,
    input                  pclk                ,
    input                  prstn               ,

    input                  psel                ,
    input  [11:0]          paddr               ,
    input                  penable             ,
    input                  pwrite              ,
    input  [31:0]          pwdata              ,
//    output                pready              ,
//    output                pslverr             ,
    output [31:0]          prdata
);

// ------------------------------------------------------------
// APB write read enable
// ------------------------------------------------------------
reg     [31:0]  ff_rdata;
wire            read_en   = psel && (~penable) && (~pwrite);
wire            write_en  = psel && (~penable) && pwrite;
wire    [11:0]  addr      = paddr;
wire    [31:0]  wdata     = pwdata;

always @(posedge pclk or negedge prst) begin
    if (!prst)
        prdata <= 32'b0;
    else if (read_en) 
        prdata <= ff_rdata[31:0];
end

// ------------------------------------------------------------
// Internal Signals
// ------------------------------------------------------------
reg             ff_cr_en            ;
reg             ff_cr_mode          ;
reg             ff_cr_outsel        ;
reg     [01:0]  ff_cr_edgesel       ;
reg             ff_cr_oten          ;
reg     [01:0]  ff_cr_otsel         ;
reg             ff_cr_pga0_ocd_en   ;
reg             ff_cr_pga1_ocd_en   ;
reg     [01:0]  ff_cr_pga0_ocd_th   ;
reg     [01:0]  ff_cr_pga1_ocd_th   ;
reg     [02:0]  ff_cr_lpf           ;
reg     [01:0]  ff_cr_hys           ;
reg             ff_cr_offset        ;
reg             ff_cr_speed         ;
reg             ff_cr1_ocd0_neg_en  ;
reg             ff_cr1_ocd0_pos_en  ;
reg             ff_cr1_ocd1_neg_en  ;
reg             ff_cr1_ocd1_pos_en  ;
reg             ff_cr1_level0_en    ;
reg             ff_cr1_level1_en    ;
reg             ff_cr1_uv15_en      ;
reg             ff_cr1_ov15_en      ;
reg             ff_cr1_uv50_en      ;
reg             ff_cr1_ov50_en      ;
reg             ff_cr1_otp_en       ;
reg             ff_cr1_adc_otp_en   ;
reg             ff_cr1_brk_io_en    ;
reg             ff_cr1_level0_pol   ;
reg             ff_cr1_level1_pol   ;
reg             ff_cr1_brkio_pol    ;
reg     [01:0]  ff_mux_phsel        ;
reg             ff_ier_ie           ;
reg             ff_ier_leve0e       ;
reg             ff_ier_leve1e       ;
reg             ff_ier_ocd0_nege    ;
reg             ff_ier_ocd0_pose    ;
reg             ff_ier_ocd1_nege    ;
reg             ff_ier_ocd1_pose    ;
reg       ff_clr_pfclr        ;
reg       ff_clr_nfclr        ;
reg       ff_clr_levf0clr     ;
reg       ff_clr_levf1clr     ;
reg       ff_clr_ocd0_negclr  ;
reg       ff_clr_ocd0_posclr  ;
reg       ff_clr_ocd1_negclr  ;
reg       ff_clr_ocd1_posclr  ;
reg     [09:0]  ff_filt_fltdiv      ;
reg     [04:0]  ff_filt_fltwin      ;
reg     [04:0]  ff_filt_fltth       ;
reg     [02:0]  ff_filt_dia_ocd_neg_filt_sel;
reg     [02:0]  ff_filt_dia_ocd_pos_filt_sel;
reg     [02:0]  ff_filt_dia_level0_filt_sel;
reg     [02:0]  ff_filt_dia_level1_filt_sel;
reg     [02:0]  ff_filt_dia_uv15_filt_sel;
reg     [02:0]  ff_filt_dia_ov15_filt_sel;
reg     [02:0]  ff_filt_dia_uv50_filt_sel;
reg     [02:0]  ff_filt_dia_ov50_filt_sel;
reg     [02:0]  ff_filt_dia_otp_filt_sel;
reg     [02:0]  ff_filt_dia_brk_filt_sel;

wire            wir_sts_out_sync    ;
wire            wir_sts_out_valid   ;
wire            wir_sts_w_out       ;
wire            wir_sts_v_out       ;
wire            wir_sts_u_out       ;
wire            wir_sts_ocd0_neg_filed;
wire            wir_sts_ocd0_pos_filed;
wire            wir_sts_ocd1_neg_filed;
wire            wir_sts_ocd1_pos_filed;
wire            wir_sts_level0_filed;
wire            wir_sts_level1_filed;
wire            wir_sts_uv15_filed  ;
wire            wir_sts_ov15_filed  ;
wire            wir_sts_uv50_filed  ;
wire            wir_sts_ov50_filed  ;
wire            wir_sts_otp_filed   ;
wire            wir_sts_brk_filed   ;
wire            wir_sr_pf           ;
wire            wir_sr_nf           ;
wire            wir_sr_levf0f       ;
wire            wir_sr_levf1f       ;
wire            wir_sr_ocd0_negf    ;
wire            wir_sr_ocd0_posf    ;
wire            wir_sr_ocd1_negf    ;
wire            wir_sr_ocd1_posf    ;
assign          wir_sts_out_sync    = sts_out_sync        ;
assign          wir_sts_out_valid   = sts_out_valid       ;
assign          wir_sts_w_out       = sts_w_out           ;
assign          wir_sts_v_out       = sts_v_out           ;
assign          wir_sts_u_out       = sts_u_out           ;
assign          wir_sts_ocd0_neg_filed= sts_ocd0_neg_filed  ;
assign          wir_sts_ocd0_pos_filed= sts_ocd0_pos_filed  ;
assign          wir_sts_ocd1_neg_filed= sts_ocd1_neg_filed  ;
assign          wir_sts_ocd1_pos_filed= sts_ocd1_pos_filed  ;
assign          wir_sts_level0_filed= sts_level0_filed    ;
assign          wir_sts_level1_filed= sts_level1_filed    ;
assign          wir_sts_uv15_filed  = sts_uv15_filed      ;
assign          wir_sts_ov15_filed  = sts_ov15_filed      ;
assign          wir_sts_uv50_filed  = sts_uv50_filed      ;
assign          wir_sts_ov50_filed  = sts_ov50_filed      ;
assign          wir_sts_otp_filed   = sts_otp_filed       ;
assign          wir_sts_brk_filed   = sts_brk_filed       ;
assign          wir_sr_pf           = sr_pf               ;
assign          wir_sr_nf           = sr_nf               ;
assign          wir_sr_levf0f       = sr_levf0f           ;
assign          wir_sr_levf1f       = sr_levf1f           ;
assign          wir_sr_ocd0_negf    = sr_ocd0_negf        ;
assign          wir_sr_ocd0_posf    = sr_ocd0_posf        ;
assign          wir_sr_ocd1_negf    = sr_ocd1_negf        ;
assign          wir_sr_ocd1_posf    = sr_ocd1_posf        ;

// ------------------------------------------------------------
// write_process
// ------------------------------------------------------------
wire     wren_cr             = write_en & (addr[11:2] == 10'h1);
wire     wren_cr1            = write_en & (addr[11:2] == 10'h2);
wire     wren_mux            = write_en & (addr[11:2] == 10'h3);
wire     wren_ier            = write_en & (addr[11:2] == 10'h4);
wire     wren_clr            = write_en & (addr[11:2] == 10'h6);
wire     wren_filt           = write_en & (addr[11:2] == 10'h7);
wire     wren_filt_dia       = write_en & (addr[11:2] == 10'h8);

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_en <= 1'h0;
    else if (wren_cr) begin
        ff_cr_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_mode <= 1'h0;
    else if (wren_cr) begin
        ff_cr_mode <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_outsel <= 1'h0;
    else if (wren_cr) begin
        ff_cr_outsel <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_edgesel <= 2'h0;
    else if (wren_cr) begin
        ff_cr_edgesel <= wdata[4:3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_oten <= 1'h0;
    else if (wren_cr) begin
        ff_cr_oten <= wdata[5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_otsel <= 2'h0;
    else if (wren_cr) begin
        ff_cr_otsel <= wdata[7:6];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_pga0_ocd_en <= 1'h0;
    else if (wren_cr) begin
        ff_cr_pga0_ocd_en <= wdata[8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_pga1_ocd_en <= 1'h0;
    else if (wren_cr) begin
        ff_cr_pga1_ocd_en <= wdata[9];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_pga0_ocd_th <= 2'h0;
    else if (wren_cr) begin
        ff_cr_pga0_ocd_th <= wdata[11:10];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_pga1_ocd_th <= 2'h0;
    else if (wren_cr) begin
        ff_cr_pga1_ocd_th <= wdata[13:12];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_lpf <= 3'h0;
    else if (wren_cr) begin
        ff_cr_lpf <= wdata[18:16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_hys <= 2'h0;
    else if (wren_cr) begin
        ff_cr_hys <= wdata[20:19];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_offset <= 1'h0;
    else if (wren_cr) begin
        ff_cr_offset <= wdata[21];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr_speed <= 1'h0;
    else if (wren_cr) begin
        ff_cr_speed <= wdata[22];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_ocd0_neg_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_ocd0_neg_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_ocd0_pos_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_ocd0_pos_en <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_ocd1_neg_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_ocd1_neg_en <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_ocd1_pos_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_ocd1_pos_en <= wdata[3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_level0_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_level0_en <= wdata[4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_level1_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_level1_en <= wdata[5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_uv15_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_uv15_en <= wdata[6];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_ov15_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_ov15_en <= wdata[7];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_uv50_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_uv50_en <= wdata[8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_ov50_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_ov50_en <= wdata[9];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_otp_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_otp_en <= wdata[10];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_adc_otp_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_adc_otp_en <= wdata[11];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_brk_io_en <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_brk_io_en <= wdata[12];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_level0_pol <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_level0_pol <= wdata[20];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_level1_pol <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_level1_pol <= wdata[21];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cr1_brkio_pol <= 1'h0;
    else if (wren_cr1) begin
        ff_cr1_brkio_pol <= wdata[22];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_mux_phsel <= 2'h0;
    else if (wren_mux) begin
        ff_mux_phsel <= wdata[1:0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ier_ie <= 1'h0;
    else if (wren_ier) begin
        ff_ier_ie <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ier_leve0e <= 1'h0;
    else if (wren_ier) begin
        ff_ier_leve0e <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ier_leve1e <= 1'h0;
    else if (wren_ier) begin
        ff_ier_leve1e <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ier_ocd0_nege <= 1'h0;
    else if (wren_ier) begin
        ff_ier_ocd0_nege <= wdata[3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ier_ocd0_pose <= 1'h0;
    else if (wren_ier) begin
        ff_ier_ocd0_pose <= wdata[4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ier_ocd1_nege <= 1'h0;
    else if (wren_ier) begin
        ff_ier_ocd1_nege <= wdata[5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ier_ocd1_pose <= 1'h0;
    else if (wren_ier) begin
        ff_ier_ocd1_pose <= wdata[6];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_pfclr <= 1'h0;
    else if (wren_clr)
        ff_clr_pfclr <= wdata[0];
    else 
        ff_clr_pfclr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_nfclr <= 1'h0;
    else if (wren_clr)
        ff_clr_nfclr <= wdata[1];
    else 
        ff_clr_nfclr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_levf0clr <= 1'h0;
    else if (wren_clr)
        ff_clr_levf0clr <= wdata[2];
    else 
        ff_clr_levf0clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_levf1clr <= 1'h0;
    else if (wren_clr)
        ff_clr_levf1clr <= wdata[3];
    else 
        ff_clr_levf1clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_ocd0_negclr <= 1'h0;
    else if (wren_clr)
        ff_clr_ocd0_negclr <= wdata[4];
    else 
        ff_clr_ocd0_negclr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_ocd0_posclr <= 1'h0;
    else if (wren_clr)
        ff_clr_ocd0_posclr <= wdata[5];
    else 
        ff_clr_ocd0_posclr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_ocd1_negclr <= 1'h0;
    else if (wren_clr)
        ff_clr_ocd1_negclr <= wdata[6];
    else 
        ff_clr_ocd1_negclr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clr_ocd1_posclr <= 1'h0;
    else if (wren_clr)
        ff_clr_ocd1_posclr <= wdata[7];
    else 
        ff_clr_ocd1_posclr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_fltdiv <= 10'h0;
    else if (wren_filt) begin
        ff_filt_fltdiv <= wdata[9:0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_fltwin <= 5'h0;
    else if (wren_filt) begin
        ff_filt_fltwin <= wdata[14:10];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_fltth <= 5'h0;
    else if (wren_filt) begin
        ff_filt_fltth <= wdata[19:15];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_ocd_neg_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_ocd_neg_filt_sel <= wdata[2:0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_ocd_pos_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_ocd_pos_filt_sel <= wdata[5:3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_level0_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_level0_filt_sel <= wdata[8:6];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_level1_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_level1_filt_sel <= wdata[11:9];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_uv15_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_uv15_filt_sel <= wdata[14:12];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_ov15_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_ov15_filt_sel <= wdata[17:15];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_uv50_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_uv50_filt_sel <= wdata[20:18];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_ov50_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_ov50_filt_sel <= wdata[23:21];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_otp_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_otp_filt_sel <= wdata[26:24];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_filt_dia_brk_filt_sel <= 3'h0;
    else if (wren_filt_dia) begin
        ff_filt_dia_brk_filt_sel <= wdata[29:27];
    end
end


// ------------------------------------------------------------
// read_process
// ------------------------------------------------------------

wire  [31:0]  wir_r_sts      = {9'h0, wir_sts_brk_filed, wir_sts_otp_filed, wir_sts_ov50_filed, wir_sts_uv50_filed, wir_sts_ov15_filed, wir_sts_uv15_filed, wir_sts_level1_filed, wir_sts_level0_filed, wir_sts_ocd1_pos_filed, wir_sts_ocd1_neg_filed, wir_sts_ocd0_pos_filed, wir_sts_ocd0_neg_filed, 6'h0, wir_sts_u_out, wir_sts_v_out, wir_sts_w_out, wir_sts_out_valid, wir_sts_out_sync};
wire  [31:0]  wir_r_cr       = {9'h0, ff_cr_speed, ff_cr_offset, ff_cr_hys[20:19], ff_cr_lpf[18:16], 2'h0, ff_cr_pga1_ocd_th[13:12], ff_cr_pga0_ocd_th[11:10], ff_cr_pga1_ocd_en, ff_cr_pga0_ocd_en, ff_cr_otsel[7:6], ff_cr_oten, ff_cr_edgesel[4:3], ff_cr_outsel, ff_cr_mode, ff_cr_en};
wire  [31:0]  wir_r_cr1      = {9'h0, ff_cr1_brkio_pol, ff_cr1_level1_pol, ff_cr1_level0_pol, 7'h0, ff_cr1_brk_io_en, ff_cr1_adc_otp_en, ff_cr1_otp_en, ff_cr1_ov50_en, ff_cr1_uv50_en, ff_cr1_ov15_en, ff_cr1_uv15_en, ff_cr1_level1_en, ff_cr1_level0_en, ff_cr1_ocd1_pos_en, ff_cr1_ocd1_neg_en, ff_cr1_ocd0_pos_en, ff_cr1_ocd0_neg_en};
wire  [31:0]  wir_r_mux      = {30'h0, ff_mux_phsel[1:0]};
wire  [31:0]  wir_r_ier      = {25'h0, ff_ier_ocd1_pose, ff_ier_ocd1_nege, ff_ier_ocd0_pose, ff_ier_ocd0_nege, ff_ier_leve1e, ff_ier_leve0e, ff_ier_ie};
wire  [31:0]  wir_r_sr       = {24'h0, wir_sr_ocd1_posf, wir_sr_ocd1_negf, wir_sr_ocd0_posf, wir_sr_ocd0_negf, wir_sr_levf1f, wir_sr_levf0f, wir_sr_nf, wir_sr_pf};
wire  [31:0]  wir_r_filt     = {12'h0, ff_filt_fltth[19:15], ff_filt_fltwin[14:10], ff_filt_fltdiv[9:0]};
wire  [31:0]  wir_r_filt_dia = {2'h0, ff_filt_dia_brk_filt_sel[29:27], ff_filt_dia_otp_filt_sel[26:24], ff_filt_dia_ov50_filt_sel[23:21], ff_filt_dia_uv50_filt_sel[20:18], ff_filt_dia_ov15_filt_sel[17:15], ff_filt_dia_uv15_filt_sel[14:12], ff_filt_dia_level1_filt_sel[11:9], ff_filt_dia_level0_filt_sel[8:6], ff_filt_dia_ocd_pos_filt_sel[5:3], ff_filt_dia_ocd_neg_filt_sel[2:0]};

always @ (*) begin
    ff_rdata = 32'h0;
    if (read_en) begin
        case (addr[11:2])
            10'b0000000000     :    ff_rdata = wir_r_sts;
            10'b0000000001     :    ff_rdata = wir_r_cr;
            10'b0000000010     :    ff_rdata = wir_r_cr1;
            10'b0000000011     :    ff_rdata = wir_r_mux;
            10'b0000000100     :    ff_rdata = wir_r_ier;
            10'b0000000101     :    ff_rdata = wir_r_sr;
            10'b0000000111     :    ff_rdata = wir_r_filt;
            10'b0000001000     :    ff_rdata = wir_r_filt_dia;
            default: ff_rdata = 32'h0;
        endcase
    end
end
// ------------------------------------------------------------
// Assign
// ------------------------------------------------------------
assign  cr_en               = ff_cr_en            ;
assign  cr_mode             = ff_cr_mode          ;
assign  cr_outsel           = ff_cr_outsel        ;
assign  cr_edgesel          = ff_cr_edgesel       ;
assign  cr_oten             = ff_cr_oten          ;
assign  cr_otsel            = ff_cr_otsel         ;
assign  cr_pga0_ocd_en      = ff_cr_pga0_ocd_en   ;
assign  cr_pga1_ocd_en      = ff_cr_pga1_ocd_en   ;
assign  cr_pga0_ocd_th      = ff_cr_pga0_ocd_th   ;
assign  cr_pga1_ocd_th      = ff_cr_pga1_ocd_th   ;
assign  cr_lpf              = ff_cr_lpf           ;
assign  cr_hys              = ff_cr_hys           ;
assign  cr_offset           = ff_cr_offset        ;
assign  cr_speed            = ff_cr_speed         ;
assign  cr1_ocd0_neg_en     = ff_cr1_ocd0_neg_en  ;
assign  cr1_ocd0_pos_en     = ff_cr1_ocd0_pos_en  ;
assign  cr1_ocd1_neg_en     = ff_cr1_ocd1_neg_en  ;
assign  cr1_ocd1_pos_en     = ff_cr1_ocd1_pos_en  ;
assign  cr1_level0_en       = ff_cr1_level0_en    ;
assign  cr1_level1_en       = ff_cr1_level1_en    ;
assign  cr1_uv15_en         = ff_cr1_uv15_en      ;
assign  cr1_ov15_en         = ff_cr1_ov15_en      ;
assign  cr1_uv50_en         = ff_cr1_uv50_en      ;
assign  cr1_ov50_en         = ff_cr1_ov50_en      ;
assign  cr1_otp_en          = ff_cr1_otp_en       ;
assign  cr1_adc_otp_en      = ff_cr1_adc_otp_en   ;
assign  cr1_brk_io_en       = ff_cr1_brk_io_en    ;
assign  cr1_level0_pol      = ff_cr1_level0_pol   ;
assign  cr1_level1_pol      = ff_cr1_level1_pol   ;
assign  cr1_brkio_pol       = ff_cr1_brkio_pol    ;
assign  mux_phsel           = ff_mux_phsel        ;
assign  ier_ie              = ff_ier_ie           ;
assign  ier_leve0e          = ff_ier_leve0e       ;
assign  ier_leve1e          = ff_ier_leve1e       ;
assign  ier_ocd0_nege       = ff_ier_ocd0_nege    ;
assign  ier_ocd0_pose       = ff_ier_ocd0_pose    ;
assign  ier_ocd1_nege       = ff_ier_ocd1_nege    ;
assign  ier_ocd1_pose       = ff_ier_ocd1_pose    ;
assign  clr_pfclr           = ff_clr_pfclr        ;
assign  clr_nfclr           = ff_clr_nfclr        ;
assign  clr_levf0clr        = ff_clr_levf0clr     ;
assign  clr_levf1clr        = ff_clr_levf1clr     ;
assign  clr_ocd0_negclr     = ff_clr_ocd0_negclr  ;
assign  clr_ocd0_posclr     = ff_clr_ocd0_posclr  ;
assign  clr_ocd1_negclr     = ff_clr_ocd1_negclr  ;
assign  clr_ocd1_posclr     = ff_clr_ocd1_posclr  ;
assign  filt_fltdiv         = ff_filt_fltdiv      ;
assign  filt_fltwin         = ff_filt_fltwin      ;
assign  filt_fltth          = ff_filt_fltth       ;
assign  filt_dia_ocd_neg_filt_sel= ff_filt_dia_ocd_neg_filt_sel;
assign  filt_dia_ocd_pos_filt_sel= ff_filt_dia_ocd_pos_filt_sel;
assign  filt_dia_level0_filt_sel= ff_filt_dia_level0_filt_sel;
assign  filt_dia_level1_filt_sel= ff_filt_dia_level1_filt_sel;
assign  filt_dia_uv15_filt_sel= ff_filt_dia_uv15_filt_sel;
assign  filt_dia_ov15_filt_sel= ff_filt_dia_ov15_filt_sel;
assign  filt_dia_uv50_filt_sel= ff_filt_dia_uv50_filt_sel;
assign  filt_dia_ov50_filt_sel= ff_filt_dia_ov50_filt_sel;
assign  filt_dia_otp_filt_sel= ff_filt_dia_otp_filt_sel;
assign  filt_dia_brk_filt_sel= ff_filt_dia_brk_filt_sel;
// ------------------------------------------------------------
// End of the module
// ------------------------------------------------------------
endmodule
